The features in integrated circuit manufacture have continued to be reduced in size, while the wavelength of the light used to print these features has remained at about 193 nm. The resolution of these features in a photoresist pattern begins to blur at a pitch of about 100 nm. To enable manufacture of integrated circuits with smaller feature sizes, double patterning techniques (DPT) have been developed.
In double patterning technology one mask with a pitch (geometry width plus space between geometries) of about 50 nm may be decomposed into two masks, each with a pitch of about 100 nm. In a single patterning technology the space between two geometries is typically limited by photolithography. By decomposing the single pattern into two patterns, spaces approximately half the space of a single pattern technology may be formed using double patterning technology resulting in a significant reduction in chip area.
One DPT method is to pattern and etch a given layer using a first mask and then to pattern and etch the same layer using a second mask. Another DPT method is to first expose the first mask in a photoresist layer and then expose the second mask in the same photoresist layer prior to etching.
DPT technology becomes especially challenging for SRAM cells where geometries are often pushed significantly below the minimum allowed design rules for random logic. Techniques used to ensure a given mask level is DPT compatible are generally inadequate for SRAM cells.
A circuit diagram of a typical 6 transistor (6-T) SRAM cell is shown in FIG. 1. The 6-T SRAM cell consists of two inverters with cross coupled gates. A first inverter is composed of pullup PMOS transistor 28 and pulldown NMOS transistor 22. A second inverter is composed of pullup PMOS transistor 34 and pulldown NMOS transistor 38. Both inverters are connected between power (Vdd) 30 and ground (Vss) 20. The gate of the first inverter 42 is connected to the storage node (SN2) of the second inverter and the gate of the second inverter 40 is connected to the storage node (SN1) of the first inverter. Pass transistor 24 connects the storage node (SN1) of the first inverter to the first bitline 26 and pass transistor 38 connects the storage node (SN2) of the second inverter to the second bitline 36. The gates of the pass transistors, 24 and 38 are connected to wordline 32.
When the voltage on SN2 is low, because SN2 is coupled to the gate 42 of the first inverter, the voltage on the gate is also low so the NMOS transistor 22 of the first inverter is off and the PMOS transistor 28 of the first inverter is on. Since the PMOS transistor 28 is connected to Vdd 30 and is turned on, the storage node of the first inverter (SN1) is charged to approximately at Vdd. SN1 is coupled to the gate 40 of the second inverter so the NMOS transistor 38 of the second inverter is on and the PMOS transistor 34 of the second inverter is off. The storage node of the second inverter (SN2) is discharged through NMOS transistor 38 to approximately ground 20.
A top-down view of the active, gate, contact, and metal1 patterns of a typical small aspect ratio (SAR) SRAM cell are shown in FIG. 2. Top-down views of the active (FIG. 3A), gate (FIG. 3B), contact (FIG. 3C), metal1 (FIG. 3D), via-1 (FIG. 3E), and metal-2 (FIG. 3F) patterns are shown in FIGS. 3A through 3F. While it may be possible to decompose the active (3A), gate (3B), contact (3C), and via-1 (3E) patterns into two patterns compatible with double patterning technology (DPT), the wiring levels metal-1 (3D) and metal-2 (3F) are not DPT compatible. It is impossible to decompose the metal-1 pattern (3D) into a two color pattern with no design rule conflicts. Likewise it is impossible to decompose the metal-2 pattern (3F) into a two color pattern with no design rule conflicts. The size of the SAR SRAM cell is therefore limited by the metal-1 and metal-2 patterns. For a 20 nm technology node the area of SAR SRAM cell is limited to about 0.08 um2 or greater.